SystemVerilog for verification : a guide to learning the testbench language features
Explains how to use the power of the SystemVerilog testbench constructs and methodology without requiring in-depth knowledge of Object Oriented Programming or Constrained Random Testing. This book covers the SystemVerilog verification constructs such as classes, program blocks, C interface, randomization, and functional coverage
eBook, English, 2008
Springer, New York, NY, 2008